The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) devices. More particularly, the present invention relates to a look-ahead, wrap-around first-in, first-out (xe2x80x9cFIFOxe2x80x9d) integrated circuit device architecture.
U.S. Pat. No. 5,996,052 issued Nov. 30, 1999 describes a conventional method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array. The design illustrated includes a FIFO memory, configured with a predetermined number of memory stages, which is incorporated into the input side of the device address decoder and is used only for writing. The write decoder circuitry of the design shown constitutes a FIFO memory and a write only address decoder.
Conventional data capturing techniques using non-look-ahead FIFOs, as represented by the ""052 patent, require extremely tight timing constraints between the data-in and clocking signals. Moreover, in order to ensure overall high speed data input/output (xe2x80x9cI/Oxe2x80x9d) operations, read-modify-write operations must be able to complete in the same time frame as read only cycles.
In order to implement such high speed data I/O operations, a write address FIFO is disclosed herein which, in an exemplary embodiment is organized as an eight stage by 6 bits configuration, that may be operated in a wrap-around fashion and wherein conventional status flags (i.e. full, half-full, empty, etc.) are not required. The particular embodiment of the FIFO of the present invention is able to operate at 714 MHz (1.4 ns cycle time) or faster and data loaded into the FIFO is available for read accessing from the output of the FIFO one cycle after it is loaded. In essence, the design disclosed serves to effectively minimize device power requirements while simultaneously enabling high speed operation utilizing separate read data and write address data paths to the memory array.
Functionally, a unique latching technique is utilized such that data is transparently captured into a FIFO stage implemented in the form of a single stage latch which functions as the storage element. More specifically, the technique disclosed herein serves to initialize the latency level of the first stage of the FIFO in the xe2x80x9cenabledxe2x80x9d (or xe2x80x9ctransparentxe2x80x9d) state whereby it becomes xe2x80x9cinactivexe2x80x9d when a load command is executed. When the load command is executed to the first stage, its latch is xe2x80x9cdisabledxe2x80x9d, but the following stage""s latch becomes xe2x80x9cactivexe2x80x9d in anticipation of the next stage being loaded by a subsequent load command. Latching in this fashion results in a single-cycle, look-ahead function.
In an exemplary embodiment, since the latching sequence operates in a single cycle look-ahead manner, it is desirable to utilize N+1 FIFO stages, where N is the stage depth of the FIFO. Using this as an example, an eight-stage FIFO would then require nine FIFO stages to implement single-cycle look-ahead functionality. This wrap-around operation can continue as long as the following condition is satisfied:
NLxe2x88x92NRxe2x89xa6T
where NL is the number of loads; NR is the number of reads and T is the logical depth of the FIFO. In other words, a nine-stage FIFO using single-cycle look-ahead provides an eight-stage logical depth and
NLxe2x88x92NRxe2x89xa68
By extending the transparent single-cycle latching technique disclosed herein, the frequency performance of a DRAM memory macro can be greatly improved at only a slight increase in power requirements through the use of two-cycle, look-ahead operation. In this manner, the timing constraints otherwise associated with enabling the latch on the same cycle as a load command occurs are removed even further increasing the ease in handling back-to-back loads and enabling even higher frequency operation.
Utilizing this technique, when a FIFO load occurs implemented with two-cycle look-ahead operation, the latching signal for the targeted stage goes xe2x80x9cinactivexe2x80x9d (i.e. capturing data or xe2x80x9cdisabled loadxe2x80x9d) while the next stage remains xe2x80x9cactivexe2x80x9d (i.e. xe2x80x9ctransparent loadingxe2x80x9d) and the latch on the following stage (two stages after the loaded stage) goes xe2x80x9cactivexe2x80x9d in such a way that there are always two stages with their latches xe2x80x9cactivexe2x80x9d (or xe2x80x9cenabledxe2x80x9d). When this two-stage transparency operation is implemented, N+2 stages are required for wrap-around operation for a FIFO stage equivalency of N stages.
Wrap-around operation in this manner then also requires:
NLxe2x88x92NRxe2x89xa6T
as for the previously described single-cycle look-ahead function. With respect to the exemplary embodiments disclosed herein, a primary difference between one-stage and two-stage look-ahead operation is the generation of the LWORDB and WWORDB signal and the number of stages in the FIFO (or CWRBIT circuits).
Particularly disclosed herein is a DRAM macro which employs only a single common set of column address inputs for reading and writing data. A write address FIFO and independent internal read and write address and data paths allow for simultaneous read/write operation which effectively doubles the data rate for read-modify-write or read-write cycles. For a read cycle, the column address is loaded into a write address FIFO for use in a later write cycle. In each clock cycle where the write address strobe (xe2x80x9cWASBxe2x80x9d) is active xe2x80x9clowxe2x80x9d, the in-coming column address is loaded into an eight stage FIFO. Although the FIFO stores eight addresses, there are nine stages, in the case of single cycle look-ahead loading, so that the load pointer can xe2x80x9clook-aheadxe2x80x9d for improved FIFO speed. In each write cycle (WRITEB xe2x80x9clowxe2x80x9d), a write address is read from the FIFO and sent to the write column decoders and a column address can be loaded into the FIFO during a read cycle. This means that the read address can be stored in the FIFO and retrieved in a subsequent write cycle without having to supply a write address to the macro. This feature provides read-modify-write operation with simultaneous read and write cycles and only the read addresses need be supplied to the macro. It should also be noted that write only cycles may also be implemented through the conjunctive use of the WASB and WRITE commands.